
library ieee;
use ieee.std_logic_1164.all;

entity jkFlipFlopTb is
end entity jkFlipFlopTb;

architecture RTL of jkFlipFlopTb is

	signal jIn, kIn, clkIn, qOut, qNotOut : bit; 
	
	component jkFlipFlop is
	port (
		j, k, clk : in bit;
		q, qnot : out bit
	);
	end component jkFlipFlop;

	for all : jkFlipFlop use entity work.jkFlipFlop; 
	
begin

	COUNTER : jkFlipFlop port map (jIn, kIn, clkIn, qOut, qNotOut);

	clkIn <= not clkIn after 10 ns;
	jIn <= '0', '1' after 20 ns, '0' after 40 ns, '1' after 60 ns, '0' after 80 ns;
	kIn <= '0', '1' after 20 ns, '1' after 40 ns, '0' after 60 ns, '0' after 80 ns;



end architecture RTL;

